The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a vertical transistor containing a top source/drain structure that is formed utilizing a low temperature epitaxial growth process.
Conventional vertical transistors are devices where the source-drain current flows in a direction normal to the substrate surface. In such devices, a vertical semiconductor pillar (or fin) defines the channel with the source and drain located at opposing ends of the semiconductor pillar. Vertical transistors are an attractive option for technology scaling for 5 nm and beyond.
Forming the top source/drain structure for vertical transistors is very challenging. Since the bottom source/drain structure and the gate structures are formed prior to the formation of the top source/drain structure, the top source/drain structure epitaxial formation is limited to temperatures lower than 550° C. Growing selective epitaxy at such low temperatures is very challenging, if not impossible. While selective growth of boron-doped silicon germanium (i.e., SiGe:B) for pFETs can be accomplished, the counterpart of selective epitaxial growth of phosphorus-doped silicon (i.e., Si:P) for nFETs does not work. Si based epitaxy at temperatures of 550° C. and below is very challenging. Using silicon germanium rather than silicon to carry the n-type dopant does not work either since the incorporation and activation of phosphorus or arsenic into silicon germanium is very low. In view of the above, there is a need to provide a method in which the top source/drain structure of at least the nFET is formed utilizing a low temperature epitaxial growth process.